1. Technical Field
The present application relates generally to an improved integrated circuit device. More specifically, the present application is directed to a programmable local clock buffer for integrated circuit devices which is capable of varying initial settings.
2. Description of Related Art
With modern high-speed integrated circuit devices clock grids are utilized for distributing a system clock signal to the various portions of the integrated circuit. The clock signal from the clock grid is commonly redistributed locally by way of local clock buffers (LCBs). A typical array circuit design block, e.g., a Segment Look-aside Buffer (SLB), Translation Look-aside Buffer (TLB), Effective to Real Address Translation (ERAT) block, or the like, uses many LCBs to distribute the clock signal throughout the design.
FIGS. 1A-1D illustrate an exemplary diagram of a known LCB structure which may be used in array designs. The LCB structure 100 has the capability to adjust the offset and pulse width of the clock signal between pre-established programmable settings. The programming of the settings of the LCB allows hardware tuning for debugging, for example.
As shown in FIGS. 1A-1D, the LCB 100 includes a first portion 110 in which there are a plurality of circuit paths 112-118 for providing different pre-established programmable offsets for an input clock signal clkg. Each circuit path 112-118 has a set of delay elements 120 which operate to delay the clock signal clkg by predetermined amounts such that differing offsets of the leading edge of the clock signal clkg are made possible. The particular circuit path 112-118 used to adjust the offset of the leading edge of the clock signal clkg may be determined based on a controller (not shown) asserting a signal along one of the circuit paths 112-118.
Similarly, a second portion 130 of the LCB 100 includes a plurality of circuit paths 132-138 for providing different pre-established programmable pulse widths of the input clock signal clkg. The circuit paths 132-138 have sets of delay elements 140 which operation to provide different points in the input clock signal clkg where the clock signal is “chopped-off,” i.e. causes the trailing edge of the input clock signal clkg to occur. The particular circuit path 132-138 used to adjust the pulse width of the clock signal clkg may be determined based on a controller (not shown) asserting a signal along one of the circuit paths 132-138.
For example, a default setting for pulse width adjustment may be to assert a signal along the circuit path 134 pw1 so as to allow adjustment for greater or smaller pulse widths. Asserting a signal along circuit path 138 pw3 disables pulse width adjustment and the pulse width of the input clock signal clkg is utilized.
As a result of the adjustments made by the LCB 100, a resulting local clock signal clkl1 is output having a desired offset and pulse width for the local circuitry. The LCB 100 may be used to provide adjustment, for example, when the initial clock setting of the input clock signal clkg causes a problem in the operation of the local circuitry, e.g., an early mode or late mode clock signal. The LCB 100 may be used to adjust the clock signal clkg so that proper operation of the local circuitry is made possible. Moreover, for a debug operation, the pulse width and offset of the input clock signal clkg may be varied using the pre-established adjustments of the LCB 100 in order to test and determine the limitations of the local circuitry.
The enable_n input is used to enable/disable the LCB 100, i.e. clkl1 will stay at a low voltage state when enable_n=1. The set0 and pw0 inputs are connected to dummy devices to satisfy checking tool requirements. That is, when the other settings are not set (i.e. set1, set2, set3, pw1, pw2, and pw3 are not set), set0 and pw0 are the default, no matter what their inputs are.
Typically, in an integrated circuit design, the same LCB structure is utilized throughout the integrated circuit design in order to control the clocks distributed to the local circuitry portions of the integrated circuit device. A problem exists in the known LCB structure, however, in that sometimes a need arises in which a different initial offset or pulse width value is needed in different LCBs within the same circuit design. That is, while the pre-established settings for the LCB 100 may be appropriate for one or more portions of local circuitry in an integrated circuit design, the pre-established settings for the LCB 100 may not be appropriate for other portions of local circuitry in the integrated circuit design, i.e. different pulse widths and offsets are needed than are able to be provided by the LCB 100.
In order to address this problem one could use a different programmable setting as the default of the LCB 100. However, in doing so, one would lose some programmable adjustment in the hardware. For example, in the example shown in FIGS. 1A-1D, there are four pulse width settings in the LCB 100. The default setting is pw1 so that one can adjust the pulse width down one setting or up one setting. The pw3 setting is used to disable the pulse width adjustment and track with the clock grid edges. If one uses a setting of pw0 or pw2 as the default, then either the capability to decrease or increase the pulse width setting in the hardware is lost.
Another possible solution is to add more pre-established programmable settings to the LCB 100 structure. However, adding more programmable settings adds significantly to the LCB 100 structure. In today's integrated circuit devices with increasing amounts of functional logic and miniaturizing of the integrated circuit devices, space available for such functional logic is at a premium. Thus, adding more pre-established programmable setting circuit structures to the LCB 100 is not generally an acceptable solution.